1. Field of the Invention
The invention in general relates to the structure and fabrication of integrated circuits and more particularly to an integrated circuit including ferroelectric components, and a process for fabrication of integrated circuits containing ferroelectric components.
2. Statement of the Problem
As is well-known, integrated circuits, sometimes called semiconductor devices, are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials which are either electrically conductive, electrically non-conductive, or electrically semiconductive. This invention relates to a semiconductor devices utilizing ferroelectric materials. The invention shall be described as implemented with lead zirconate titanate (PZT), a ferroelectric material of the Perovskite structure and which is most commonly used in ferroelectric integrated circuits; however, it may also be implemented utilizing other ferroelectric materials, such as those described in U.S. patent application Ser. No. 807,439.
The semiconducting material out of which the wafer and other parts of integrated circuits are fabricated is generally either silicon (Si) or gallium arsenide (GaAs). Since silicon is the most commonly used material, the invention shall be described in terms of silicon technology, although the invention is also applicable to semiconductor technologies based on GaAs or other semiconductors. Silicon can be used in either the single crystal or polycrystalline form in integrated circuits. In the integrated circuit fabrication art, polycrystalline silicon is usually called "polysilicon" or simply "poly", and shall be referred to as such herein. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as p-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant charge carriers and the doped silicon is referred to as n-type silicon. Silicon dioxide is commonly used as an insulator in silicon-based semiconductors devices. Its use is so universal that in the integrated circuit art it is often referred to as simply as "oxide". Another common silicon-based structure is called polycide. This is a composite, layered material comprising a layer of metal silicide and a layer of polysilicon. CMOS (Complimentary Metal Oxide Semiconductor) technology is currently the most commonly used integrated circuit technology, and thus the present invention will be described in terms of silicon-based CMOS technology, although it is evident that it may be utilized in other integrated circuit technologies.
The invention shall also be implemented in one of the most common, simple, and most dense integrated circuit devices, the DRAM (Dynamic Random Access Memory). DRAM circuits comprise arrays of memory cells, each cell comprising two main components: a field effect transistor (FET) and a capacitor. In the most common circuit designs, one side of the transistor is connected to one side of the capacitor, the other side of the transistor and the transistor gate are connected to external connection lines called the bit line and word line, respectively. The other side of the capacitor is connected to a reference voltage. Information is stored in the individual cell by placing a voltage across the capacitor which causes it to store a charge. The transistor provides a switch to access the capacitor. Thus the fabrication of the DRAM cell essentially comprises the fabrication of a transistor, a capacitor, and three contacts to external circuits.
A term that is often used in the art of fabrication of integrated circuits, and particularly DRAMs, is "active area" (A.A.). An active area is an area in a integrated circuit to which electrical connection is to be made. A common intermediate structure during the fabrication process of conventional DRAMs, is one in which one or more source/drain active area regions of a FET are exposed via holes in the wafer surface, while the areas adjacent the active areas are covered with silicon dioxide or other insulator. The DRAM capacitors are conventionally formed in these regions by laying down the bottom capacitor electrode layer, the capacitor dielectric layer, and the top capacitor electrode layer, while shaping the layers with a series of etch and/or mask processes to form a convoluted capacitor structure that has a large area. The final dimensions of the capacitor are then defined in one or more mask steps. The resulting capacitor overlies the area around the active area hole and the electrical connection to the bottom electrode is made through the hole to the active area. Such capacitor structures are sometimes called oversize capacitors against contact holes.
It has been known for many years that ferroelectric materials potentially offer significant advantages in integrated circuits, particularly integrated circuit memories. For example, the lowest cost, highest capacity integrated circuit memories, including conventional DRAMs, are volatile memories, that is, information stored in the memories remains only so long as power is applied to the integrated circuit. Currently available non-volatile memories, such as EPROMS or flash-type memories, are relatively costly, have relatively low storage density, require extremely high voltage applied for long periods to write and erase data, and generally have a more limited erase and write lifetime than DRAMs. It has long been recognized that ferroelectric materials have polarization states that can be selected or switched by application of an electric field, and that these polarization states remain after the electric field is removed. It is well-known that if a ferroelectric capacitor is substituted for the conventional silicon dioxide dielectric capacitor in the DRAM, instead of simply storing a charge that leaks off quickly, the capacitor can be switched between selected polarization states that will remain indefinitely after power is removed. Thus ferroelectric materials offer the possibility of simple, low cost, high density, non-volatile memories. Further, many semiconductor materials and devices, and in particular the low cost, high, capacity memories such as conventional DRAMs, are susceptible to damage or alteration of their states from radiation. It is well-known that ferroelectric materials are highly resistant to radiation damage and that their ferroelectric states are highly resistant to being altered by radiation. In addition ferroelectric memories do not need high voltage for writing or erasing, and can be written to or erased as fast as conventional memories can be read. Thus, considerable research and development has been directed toward the design and manufacture of an integrated circuit memory utilizing the switchable property of ferroelectric materials. Such memories are described in U.S. Pat. No. 2,695,396 issued to Anderson, U.S. Pat. No. 4,144,591 issued to Brody, U.S. Pat. No. 4,149,301 issued to Cook, and U.S. Pat. No. 4,360,896 issued to Brody. However, for many years no commercially successful integrated circuit memory utilizing ferroelectric switching was produced because the ferroelectric materials tended to be incompatible with the semiconductor materials and structures used in integrated circuits. When the ferroelectric materials were combined with the conventional materials in conventional integrated circuit structures, they either damaged the semiconductor materials or their ferroelectric properties were altered. Further, the ferroelectric materials memories tended to be unreliable due to fatigue of the ferroelectric material under repetitive switching, and retention of the polarization state.
Recently, more practical integrated circuits utilizing ferroelectric materials have been designed. U.S. Pat. No. 5,046,043 issued to Miller et al. discloses a DRAM memory utilizing a ferroelectric switching capacitor. In one embodiment Miller et al. solve the problem of incompatibility between ferroelectrics and the materials and structures of the silicon-based integrated circuit technology by isolating the ferroelectric capacitor from the silicon materials with a thick layer of silicon dioxide (SiO.sub.2) plus a silicon nitride barrier layer, plus an isolation layer of titanium dioxide (TiO.sub.2). In a second embodiment, the ferroelectric capacitor is separated from the sensitive MOSFET gates with thick layers of silicon dioxide and phosphorus glass and from the doped silicon active areas with a thick layer of titanium tungsten (TiW). In a third embodiment, the ferroelectric capacitor is separated from the sensitive MOSFET gates with the silicon nitride barrier and titanium dioxide isolation layers while separating the ferroelectric capacitor from the doped silicon active areas with a layer of metal, such as titanium or titanium nitride. While this disclosure solves some of the prior problems, the resulting integrated circuits and fabrication methods remain relatively complex. In the first embodiment the ferroelectric capacitors are well removed from the MOS structures, resulting in relatively low densities, and six photo-mask steps are required to form the ferroelectric capacitor; in the second embodiment the number of photo-mask steps is reduced to two, but the ferroelectric capacitors remain well removed from the MOS structures; in the third embodiment the structure is more compact, but at least seven photo-mask steps are required to form the ferroelectric capacitor. As is well-known, a photo-mask step is a relatively complex and expensive process comprising creating a photolithographic mask containing the pattern of the parts to be fabricated, coating the integrated circuit wafer with a light-sensitive material called photoresist or resist, exposing the resist-coated wafer to ultraviolet light through the mask to soften or harden parts of the resist depending on whether positive or negative resist is used, removing the softened parts of the resist, etching the wafer to remove the part unprotected by the resist, and stripping the remaining resist. As a result the ferroelectric integrated circuits produced according to the Miller et al. disclosure remain relatively high cost specialty items.
The advantages of building integrated circuits compactly so that more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds, is obtained. In addition, the business of fabricating semiconductor devices is a competitive, high-volume business. Thus manufacturing efficiency is highly important. Product quality and reliability are also highly important. It is well-known in the art that reducing the number of mask steps in the integrated circuit manufacturing process not only reduces manufacturing costs and time but also generally increases the quality and reliability of the end product, since the opportunities for disabling defects to occur are reduced. This in turn feeds back into further reduced manufacturing costs since scrapped product is reduced. Thus, a ferroelectric integrated circuit structure and process that not only permits more compact devices but also reduces the number of fabrication steps, particularly the number of mask steps, would be a significant advance in the art.
Japanese Patent No. 2-304796 discloses a more compact structure using fewer mask steps. According to this disclosure, a ferroelectric capacitor is deposited directly on the source/drain active area region of the MOS transistor. The bottom conductive layer in contact with the active area is platinum silicide (PtSi) or other metal silicide. The ferroelectric layer is deposited on the bottom electrode, then, to separate the ferroelectric material from the MOS transistor, the ferroelectric material is etched back so that it covers only the contact area. This process does not provide a reliable ferroelectric capacitor since the ferroelectric properties are diminished by interdiffusion and alloying with the PtSi or other metal silicide and the capacitor is limited to the size of the source/drain area which is very small.
The article "Integrated Ferroelectrics" by J. F. Scott, C. A. Paz De Araujo, and L. D. McMillian in Condensed Matter News, Vol. 1, No. 3, 1992, pp. 16-20, provides an overview of the current state of the art in ferroelectric integrated circuits. It lists at least 16 current developmental programs in integrated ferroelectric devices. None of these programs have yet provided a high-density, simple, easily fabricated device. Thus there remains a need for a ferroelectric integrated circuit structure and fabrication method that results in reliable, low cost, high density integrated circuit devices.
In addition to the switched capacitor structure described above, the "Integrated Ferroelectrics" article lists true ferroelectric field effect transistors, high capacity dynamic random access memories, CCD multiplexer read-out systems, integrated pyroelectric detectors, integrated surface acoustic wave devices, spatial light monitors, and microwave devices as devices that now exist in which ferroelectrics are fully integrated into Si or GaAs chips. Thus, it is evident that the disclosure of apparatus and methods for more easily fabricating a reliable, high density, ferroelectric switched capacitor DRAM implemented in silicon technology should have applications across a wide range of ferroelectric devices.
3. Solution to the problem
The present invention provides a barrier layer that permits the fabrication of compact, reliable integrated circuit structures.
The barrier layer preferably comprises one or more of the following materials: titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo) or chromium (Cr). However, the process permits the use of other materials which prevent interdiffusion between the ferroelectric components and the conventional integrated circuit components.
A key aspect of the solution to the problem has been the discovery or recognition that a ferroelectric capacitor on silicon dioxide or other insulator has good ferroelectric properties.
The invention provides an oversized capacitor against an active area contact hole. The invention provides a ferroelectric capacitor overlaid on a conducting barrier layer over the active area and adjacent regions. It has been found that while the ferroelectric properties of the ferroelectric capacitor in the contact region remain poor, the ferroelectric properties of the capacitor in the adjacent insulator-covered regions are good. Thus, the discovery permits the formation of ferroelectric capacitors of in essentially the same location as conventional capacitors in DRAMs. As a result, reliable ferroelectric DRAMS with essentially the same density as conventional DRAMs become possible.
An thin layer of contact material may be formed over the contact area prior to laying down the barrier layer to improve the ohmicity of the contact between the barrier layer and the active area.
The invention also provides a simple fabrication method to obtain the above structure. According to the method of the invention, the barrier layer, the capacitor bottom electrode layer, the ferroelectric layer, and the capacitor top electrode are laid down in subsequent layers on the conventional silicon wafer with exposed active areas. Then a single mask step is used to define the capacitor and barrier layer. Thus the fabrication process of the invention is one of relatively low cost.
In several embodiments the barrier layer itself is used as the bottom electrode. This further simplifies the fabrication method.
It has also been discovered that if a silicon-based material, such as polysilicon, a silicide, or polycide is used as a bottom electrode, a top electrode, or both, then good ferroelectric properties result. The silicon-based material can be applied directly to the active area. Thus a silicon-based material can also act as a barrier layer. In some cases, in the process of annealing the ferroelectric material a thin silicon dioxide or other insulative layer is formed between the electrode and the ferroelectric material. Preferably, the insulative layer should be 5 nm or less to prevent the formation of a parasitic capacitor.
In addition it has been discovered that good ferroelectric properties result in a structure comprising a bottom electrode, a top electrode, or both top and bottom electrodes made of a conductive oxide such as indium tin oxide (InSnO), tin dioxide (SnO.sub.2), ruthenium oxide (Ru.sub.2 O.sub.3) and others. The conductive oxide may be applied directly to the active area. It is believed that the oxygen ions in the conductive oxide compensate for an oxygen deficiency region at the ferroelectric interface such that the Fermi-level of the bottom electrode remains inside the interface layer. This results in the charge compensation occurring almost entirely outside of the electrode. Thus these conductive oxide materials also can act as a barrier layer.
The invention also provides a method of preventing shorts between the top and bottom electrodes of the ferroelectric capacitor that may be used with any of the above structures. In one aspect of the method an extra mask process is used to create a step at the edge of the capacitor so that the top electrode is narrower that the bottom electrode. In another aspect of the method a tapered edge is formed.
The present invention is particularly applicable to DRAM in that it provides a process for efficiently forming a capacitor of large area. However, once the methods of providing a transition between the conventional integrated circuit materials and the ferroelectric materials and the other features are understood as they are implemented in DRAMs, it is evident that it can be applied in other circuits also.